![]() Hence, block-owners do not have to put much effort to converge interface timing. A chip-level STA person will always put more margins for interface timing at block-level in the form of higher external delay or higher uncertainties than desired during the timing budgeting. Internal - Clk2Clk timing is always a priority for block-owners working on blocks as compared to the interface timing. Keywords: IO timing (Input & Output timing), WNS(Worst Negative Slack), TNS(Total Negative Slack), FEP(Failing End Point), ns(nano-second), ps(pico-second), PT(Prime Time). We have used Cadence Innovus as our PnR and Synopsys Primetime as our Sign-off timing tool. ![]() In this article, we will address the challenges faced while fixing the interface timing and the solutions to overcome these challenges. Interface timing of a block is as critical as the internal timing. Timing closure of a semiconductor chip is the primary concern for any physical design engineer. Interface Timing Challenges and Solutions at Block Levelīy Manish Kumar Sagarvanshi (Technical Lead), Madhav Shah (Technical Lead) eInfochips - An Arrow Company
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